Fabrication of more highly integrated nonvolatile semiconductor memory devices can be made more difficult by a corresponding reduction that can occur in available memory cell current and coupling ratio of the memory cell structures as their integration density is increased. Reduction of memory cell current can become particularly severe in NAND type nonvolatile memory devices in which a plurality of memory cells are connected in series. As illustrated in FIG. 1, a NAND type nonvolatile memory device includes a select transistor and a plurality of memory cells that are connected in series. Gate electrodes of the memory cell are connected to a word line WL. Gate electrodes of the select transistor are connected to either a ground select line GSL or a string select line SSL. A plurality of strings of series connected memory cells are connected to a common source line CSL. Each string of series connected memory cells are connected to a different bit line BL.
To perform a write operation to a selected memory cell “A”, a program voltage is applied to a gate electrode of the memory cell “A” and a voltage of 0V is applied to a channel of the memory cell “A”, which results in FN tunneling. Through FN tunneling, a logical value of “0” is stored in the selected memory cell “A” while a channel of an unselected memory cell “B” connected to a selected word line WL is floated. A voltage at least as large as that applied to a corresponding string select line SSL is applied to a selected bit line BL, and a voltage of 0V is applied to an unselected bit line BL. A program voltage is applied to a selected word line WL, and a pass voltage is applied to an unselected word line WL.
In order to prevent an unselected memory cell from being written by applied program voltages and pass voltages, a channel of an unselected memory cell connected to a selected word line WL must be floated and boosted to a predetermined voltage. However, the channel voltage of an unselected memory cell may not be sufficiently boosted due to variation in a threshold voltage of the unselected memory cell and/or the select transistor coupled to the unselected memory cell. Variation of the threshold voltage may be caused by, for example, variation in the coupling ratio and available channel voltage of the unselected memory cell and/or the select transistor. Consequently, the program and pass voltages can be constrained below a level that is sufficient for some programming speeds.
To perform a read operation, a voltage of 0V is applied to a selected word line WL and a pass voltage is applied to an unselected word line WL. A current flowing on a selected bit line BL is measured to sense data stored in the selected memory cell as a logical value of ‘0’ or ‘1’. Reading of data on the selected BL line can be facilitated by a larger sensed change in the current from the selected memory cell. However, the current that can flow through the series connected selected and unselected cells decreases with a reduction in size of the cells, which can limit higher integration of the memory device.
A nonvolatile storage device is disclosed in U.S. Pat. No. 6,222,796 entitled “NONVOLATILE SEMICONDUCTOR STORAGE DEVICE HAVING BURIED ELECTRODE WITHIN SHALLOW TRENCH”, in which a voltage is applied to an electrode buried in a trench to prevent erroneous writing. This nonvolatile storage device will now be described with reference to FIG. 2A and FIG. 2B.
As illustrated in FIG. 2A and FIG. 2B, an insulation layer 16 is in a lower portion of a shallow trench 14 in a substrate 11. A buried electrode 18 is on the insulation layer 16. A floating gate 17 is formed on an active region between the shallow trenches 14. An intergate dielectric 20 is on the floating gate 17 and the buried electrode 18. A control gate electrode 21 is on the intergate dielectric 20 and crosses over the floating gate 17 and the buried electrode 18. The buried electrode 18 extends parallel to and partially within the shallow trench 14. In the illustrated storage device, during a write operation a high-level voltage is applied to the buried electrode 18 of a memory cell that is connected to an unselect bit line to avoid writing. A thick insulation layer 19 is between the buried electrode 18 and the control gate electrode 21 to insulate the buried electrode 18 from the control gate electrode 21.
With reference to FIG. 2A, forming the buried electrodes 18 in such memory cells and providing the necessary voltages thereto can be difficult. The memory device includes source contacts 42 and bit line contacts 43 formed in an active region 41. The source contacts 42 are configured to conduct a voltage to a source region of the memory cells. The bit line contacts 43 are electrically coupled to bit lines BL. The storage device uses polysilicon contacts 44 to apply a voltage to a buried electrode 18. The regions that are used to form these various contacts can increase the area used by the cell arrays, and a peripheral circuitry is needed to supply the various voltages through the contacts further increases the area of the memory device.